Part 3: DSP280x_ECan.c
The F2808 DSP supports up to two eCAN modules, eCAN-A and eCAN-B. DSP280x_ECan.c defines functions that properly initialize the eCAN and corresponding GPIO registers for each module. These functions are:
void InitECana(void);
void InitECanb(void);
void InitECanaGpio(void);
void InitECanbGpio(void);
As the function prototypes indicate, each module has its own corresponding functions. The following is a quick look at eCAN-A’s functions (which are fairly well commented). In the InitECanx functions, eCAN-B’s function is identical to eCAN-A’s except for the particular ECAN_REGS instance used. The InitECanxGpio functions are also very similar and the small difference between them will be explained shortly.
InitECana()
/* Create a shadow register structure for the CAN control registers.
This is needed, since, only 32-bit access is allowed to these registers.
16-bit access to these registers could potentially corrupt the register contents.
This is especially true while writing to a bit (or group of bits) among bits 16 - 31
*/
struct ECAN_REGS ECanaShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for eCAN transmissions
using eCAN regs */
ECanaRegs.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANRIOC.bit.RXFUNC = 1;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
This section of code is fairly self explanatory. The first two lines declare a shadow structure and turns register write protection off (see Part 2: eCAN Programming Conventions for more information). The next two lines set bits that enable TX and RX functionality on the eCAN module. The last set of lines sets the Standard [CAN] Compatibility Bit (SCB). With this bit set, the module is in eCAN mode which gives it additional functionality (like access to all 32 mailboxes) over regular CAN.
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
...
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon cleared and are cleared again
// as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
Here, the code is simply clearing bits that could be in an unknown state when the module is powered up. Note that for the TAn, RMPn, GIFn bits, the bits must be set (a ‘1’ must be written to them) order to clear them. This is occurs in other registers as will be shown later.
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
while(ECanaShadow.CANES.bit.CCE != 1 ) // Wait for CCE bit to be set..
{ECanaShadow.CANES.all = ECanaRegs.CANES.all;}
ECanaShadow.CANBTC.all = 0;
ECanaShadow.CANBTC.bit.BRPREG = 9;
ECanaShadow.CANBTC.bit.TSEG2REG = 1;
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
while(ECanaShadow.CANES.bit.CCE != 0 ) // Wait for CCE bit to be cleared
{ECanaShadow.CANES.all = ECanaRegs.CANES.all;}
The above lines set up the timing for the eCAN module, which determines, among other things, the baud at which it operates. Before this can be accomplished though, the CPU must get permission to change the modules configuration. This is done by setting the Change Configuration Request (CCR) bit. The CPU must then wait until the Change Configuration Enable (CCE) bit is set before proceeding. After the various timing-related values are set, the CPU signals that it is done its modifications by clearing the CCR bit. It must then wait until CCE bit is cleared.
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
The last two lines of this function disables all the mailboxes so they can be configured later, and turns back on CAN register write protection via the EDIS macro.
InitECanaGpio()
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANTXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANRXA operation
EDIS;
Before examining the code about, a brief description of the way the F2808 DSP utilizes its ‘multiplexed’ GPIO pins is necessary. Besides just being normal GPIOs, many of the pins are multiplexed to serve a specific function for a particular peripheral. For instances, GPIO pin 12 can either serve as a GPIO, an eCAP IO, or the CANTX pin for eCAN-B. Therefore, prior to using a peripheral, its corresponding GPIO pins must be configured. The last two lines of code before the EDIS macro set bits in the appropriate GPIO MUX registers to accomplish this. The other lines of code (looking from the bottom, up) indicate that the pins should not be synchronized with the SYSCLKOUT (the eCAN modules handle their own synchronization) and set bits that enable the pull-up registers for GPIO pins used by module.
The big difference between InitECanaGpio() and InitECanbGpio() is that eCAN-B has more possible GPIO pins to use for its CANTX and CANRX, although only one pair may be used. In the InitECanbGpio() definition, there are several lines of code commented out. These correspond to the GPIO pins not being used for eCAN-B. If the reader intends to use eCAN-B in their project, he or she will need to check that the lines of code not being selected correspond to the GPIO pins actually being used by the hardware configuration.
Continue to Part 4, Setting Up eCAN...
