Part 4: Setting Up eCAN
The following code demonstrates the very basics of how to set up eCAN. Suggestions as to code for actually transmitting or receiving data will be covered in the sections to follow. Note that in this example, only the eCAN-A module is being used. To use the eCAN-B module instead of or in conjunction with eCAN-A, simply use the ECanbRegs structure as opposed to ECanaRegs. Also note that while both transmitting and receiving will be covered, the topics of message acceptances masks, extended message identifiers, Remote Transmission Request (RTR), and auto answer mode will not.
struct ECAN_REGS ECanaShadowLocal;
struct ECAN_MBOXES ECanMboxShadow;
The first part of code declares the shadow structures that will be used to access the eCAN registers. These should be added near the top of the main source file, before any functions. The rest of the code in this section goes into main() or some other suitable function.
InitSysCtrl();
InitECanaGpio();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
// Initialize the CAN bus and set parameters
InitECana();
Along with some general initialization, the two eCAN specific ones above are InitECanaGpio() and InitECana() (see
Part 3: DSP280x_ECan.c for more information). These must be called before any other eCAN related code will work properly.
ECanaRegs.CANME.all = 0x00000000; // Disable all mailboxes
// Transmitting MBOX1
ECanMboxShadow.MBOX1.MSGID.bit.STDMSGID = 0xFF;
ECanaMboxes.MBOX1.MSGID.all = ECanMboxShadow.MBOX1.MSGID.all;
// Receiving MBOX2
ECanMboxShadow.MBOX2.MSGID.bit.AAM = 0; // auto answer mode off
ECanMboxShadow.MBOX2.MSGID.bit.AME = 0; // acceptance mask disable
ECanMboxShadow.MBOX2.MSGID.bit.IDE = 0;
ECanMboxShadow.MBOX2.MSGID.bit.STDMSGID = 0xFF;
ECanaMboxes.MBOX2.MSGID.all = ECanMboxShadow.MBOX2.MSGID.all;
The first line of code above disables all mailboxes so that they can be configured. The next two lines of code set the message ID for Mailbox 1, which will later be configured as a transmitting mailbox. The lines following that begin the process of setting up Mailbox 2 as a receiving mailbox. Note that the line which clears the Identifier Extension (IDE) bit actually works in conjunction with the Acceptance Mask Identifier (AMI) extension bit in the Global Acceptance Mask (CANGAM) register. With the AMI bit cleared, the IDE alone determines if standard or extended message identifiers are accepted. Since the AMI bit is cleared by default, clearing the IDE bit will block extended identifiers from being received in this mailbox. The message identifier that will need to be matched for messages to be received in this mailbox is also set.
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD1 = 0; // Mailbox 1 : transmitting mailbox
ECanaShadow.CANMD.bit.MD2 = 1; // Mailbox 2 : receiving mailbox
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
// Enable Mailboxes
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME1 = 1;
ECanaShadow.CANME.bit.ME2 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 4;
ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 4;
ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0;
ECanaMboxes.MBOX2.MSGCTRL.bit.RTR = 0;
This section of code is straightforward. The first part sets/clears the Mailbox Direction (MDx) bit for each mailbox. As commented, setting the bit allows the mailbox to receive and clearing it allows it to transmit. The next part actually enables the mailboxes (remember they needed to be disabled to perform the configuration shown above). After this, the Data Length Code (DLC) is set. This represents how many bytes will be sent from this mailbox or received into it and must be a value between 1 and 8. Finally, the Remote Transmission Request (RTR) bit is cleared to disable that functionality.
EALLOW;
ECanaShadow.CANGIM.all = ECanaRegs.CANGIM.all;
ECanaShadow.CANGIM.bit.MTOM = 0;
ECanaShadow.CANGIM.bit.TCOM = 0;
ECanaShadow.CANGIM.bit.AAIM = 0;
ECanaShadow.CANGIM.bit.WDIM = 0;
ECanaShadow.CANGIM.bit.WUIM = 0;
ECanaShadow.CANGIM.bit.RMLIM = 0;
ECanaShadow.CANGIM.bit.BOIM = 0;
ECanaShadow.CANGIM.bit.EPIM = 0;
ECanaShadow.CANGIM.bit.WLIM = 0;
ECanaShadow.CANGIM.bit.GIL = 0; // Map global interrupts to ECAN0INT
ECanaShadow.CANGIM.bit.I1EN = 0;
ECanaShadow.CANGIM.bit.I0EN = 1;
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
EDIS;
Here, the Global Interrupt Mask (CANGIM) register is being configured. There five bits in this register correspond to five different interrupts. In addition to these there are six addition global interrupts that can be sent to one of two different interrupt lines (ECAN0INT or ECAN1INT). The Global Interrupt Level (GIL) bit selects which of these lines those interrupts are mapped. The Interrupt X Enable (IxEN) pins enables these interrupt lines and therefore must reflect the line selected by the GIL pin.
Before continuing, it is worth explaining, very briefly, how the interrupts work. When an interrupt is triggered, it must be handled and its corresponding bit cleared before other interrupts are processed. Besides the system interrupts configured above (which incidentally are all being ignored in this code for simplicity, hence their masking bit is cleared), there are also mailbox interrupts. The two interrupt lines mentioned above also correspond to two levels of priority with ECAN0INT being the higher of the two. Therefore, it makes sense to put system interrupts and mailbox interrupts from mailboxes which receive critical messages on ECAN0INT and the rest of the mailbox interrupts on ECAN1INT.
EALLOW;
ECanaRegs.CANMIM.all = 0x00000006;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.DBO = 0;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
EDIS;
ECanaRegs.CANMIL.all = 0xFFFFFFFF; // Mailbox Interrupt Level: All
ECanaRegs.CANOPC.all = 0x00000000;
This code deals with configuring the mailbox interrupts just discussed. The first line after the EALLOW macro configures the Mailbox Interrupt Mask (CANMIM) register. Since the only two mailboxes being used are 1 and 2, they are the only mailboxes whose interrupts will be enabled. The next line sets the Data Byte Order (DBO) to MSB first. Whether this bit should be set or cleared will depend on the particular application. The line following the EDIS macro configures the Mailbox Interrupt Level (CANMIL) register so that mailbox registers are put on the ECAN1INT line. The last line clears all the bits in the Overwrite Protection Control (OPC) register, with each bit corresponding to a specific mailbox. With this bit cleared, the data put into a receive mailbox has the potential of being lost if another message is received that cannot be put into any other mailbox. Setting the bit will keep this from happening (at the risk of losing the new incoming message).
That concludes the general procedure for setting up and configuring eCAN. The following section describes the procedure for transmitting and receiving messages.
Continue to Part 5, Transmitting and Receiving Messages...
